The present invention relates in general to integrated circuit testing and, more particularly, to reflowing solder pads on an integrated circuit die following probe test.
In the prior art during manufacturing, solder pads are disposed on the integrated circuit (IC) die and reflowed into solder bumps shaped as a half hemisphere. The solder bumps are used to flip-chip interconnect the IC die into end user systems. The flip-chip interconnect technique saves having to use conventional plastic dual in-line or surface mount packages which are much larger than the IC die. The solder bumps perform a similar function as wire bonding in conventional IC packaging to electrically interconnect the IC die to the outside world. The flip-chip die is placed facing the printed circuit board and the solder bumps are reflowed to ensure conductivity to the interconnect channels on the printed circuit board.
During the manufacturing process, a functional test of the IC die typically occurs before final inspection and shipping. In the prior art, testing is performed after the reflow process. A test set inserts a plurality of probe needles into the solder bumps to perform an electrical functional test of the integrated circuit die prior to final inspection and assembly. The testing is often performed at multiple temperatures, e.g. 150.degree. C. and -40.degree. C., to test the integrated circuit die over a full range of operating conditions. Thus, the solder bumps may be pierced a number of times during the testing procedure. The solder bumps become gouged when the test probes are inserted into heated solder bumps. Alternately, a sliding defect can occur when the test probes slide off cold solder bumps.
Another problem occurs from variability in probe contact to the solder bumps during electrical testing. It is difficult to consistently contact the test probes to all the solder bumps simultaneously because of variations in their rounded shape. Consequently good devices may be rejected as failures. In addition to erroneous electrical test yield losses, there are valid inspection yield losses associated with visual rejects if the solder bumps have excessive damage due to probe testing.
Hence, a need exists to functionally test the IC die without damaging the solder bumps.